Title

Fault Tolerant VLSI Design Using Error Correcting Codes

Creator

Hartmann, C. R. P.

Ali, A. M.

Ganguly, S.

Visweswaran, G. S.

Lala, P. K.

Publisher

Griffiss Air Force Base, NY : Rome Air Development Center, Air Force Systems Command

Date

1989

Identifier

ADA208337

ADA208337

Abstract

Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

Date Issued

1989-02

Extent

67

Corporate Author

Syracuse University

Laboratory

Rome Air Development Center

Report Number

RADC-TR-88-321

Contract

F30602-81-C-0169

DoD Project

2338

DoD Task

233801

Distribution Conflict

No

Access Rights

APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED.

Photo Quality

Not Needed

Distribution Classification

1

DTIC Record Exists

Yes

Report Availability

Full text available by request

Provenance

Motorola Mobility

Type

report

Format

67 pages ; 28 cm.